Investing in the AI Supply Chain

A top-down map from model companies to the materials beneath the fabs

The artificial intelligence buildout is not one trade. It is a stacked supply chain where demand originates at the top, when model and cloud companies commit capital, and propagates downward through chip designers, foundries, equipment makers, and finally the handful of firms that supply the materials and subsystems no one can replace. Each layer carries a different margin profile, a different competitive structure, and a different sensitivity to the cycle. This piece walks the stack from top to bottom, names the players at each level, explains how a chip is actually manufactured, and lays out a framework for thinking about where the durable economics sit.

Part I. Why a top-down map

Money in this industry flows in one direction and risk flows in the other. The cash that funds the entire chain is generated at the top, by hyperscalers and model companies whose capital spending sets the pace for everything below them. When a cloud provider commits tens of billions of dollars to data centers, that signal travels down through accelerator orders, foundry wafer starts, lithography tool bookings, and eventually orders for photoresist and specialty gases.

The competitive structure inverts as you descend. At the application layer there are dozens of credible players. By the time you reach the bottom, deep in the equipment and materials layers, you often find one company that matters, or two or three at most. Pricing power tends to concentrate where the alternatives disappear. The tradeoff is cyclicality: the deeper layers are further from the end customer and tend to swing harder when the capital spending cycle turns.

A useful way to read the map is to ask three questions at every layer. How many companies can actually do this? How much of the value do they capture? And how exposed is that revenue to a single customer, a single geography, or a single technology transition?

Part II. The stack, top to bottom

Layer 1: Model and hyperscaler companies

These are the demand creators. Their capital budgets are the headwater of the whole system, and their willingness to keep spending is the single most important variable for everyone downstream.

Frontier model labs. OpenAI and Anthropic, both still private, but central to demand through their compute commitments. Google DeepMind, Meta AI, xAI, and Mistral are the labs embedded in or backed by larger platforms.

Hyperscalers and cloud, the capital spending engines. Microsoft, Amazon, Google, and Meta together drive the majority of frontier-scale data center investment. Oracle, CoreWeave, and Nebius make up the fast-growing neocloud and GPU-cloud tier.

Custom silicon designed in-house by the hyperscalers. Google TPU, Amazon Trainium and Inferentia, Microsoft Maia, and Meta MTIA, all efforts to reduce dependence on merchant accelerators.

Application and enterprise software. Palantir, ServiceNow, Salesforce, and Adobe are the layer that monetizes AI capability for end customers.

Layer 2: Fabless chip designers and IP

This layer designs the silicon but owns no fabs. It is where brand, software ecosystems, and architecture create some of the widest moats in the chain. It also contains a quiet sublayer, the design-tool and IP vendors, whose software sits underneath every chip the others produce.

Merchant GPUs and accelerators. Nvidia is the dominant training and inference platform, with CUDA as the lock-in. AMD is the principal merchant alternative on both GPU and server CPU fronts.

Custom ASIC and networking silicon. Broadcom is the leading partner for hyperscaler custom accelerators and a networking powerhouse. Marvell is a second major custom-silicon and interconnect designer. Arista Networks supplies the high-speed Ethernet switching fabric that ties AI clusters together.

AI-native silicon startups. Cerebras went public in May 2026, while Groq, SambaNova, and Tenstorrent remain private. Each pursues an architecture distinct from the GPU.

Architecture and design-tool licensing, the layer under the layer. Arm, whose instruction set underlies most custom CPU cores. Cadence and Synopsys, the electronic design automation duopoly whose software is used to design essentially every advanced chip above.

Layer 3: Foundries and memory makers

This is where designs become physical silicon. It is extraordinarily capital intensive, and the leading edge has narrowed to a very small number of names. Memory belongs here too, and in the AI era one memory product, high-bandwidth memory, has become a genuine bottleneck.

Leading-edge logic foundries.

Memory. SK Hynix is currently the front-runner in high-bandwidth memory, the stacked DRAM that sits beside AI accelerators. Micron is the U.S.-based memory maker and an HBM supplier into the AI accelerator roadmap. Samsung competes across both DRAM and HBM in addition to its foundry business.

High-bandwidth memory deserves singling out. The bandwidth between an accelerator and its memory often constrains real-world AI performance more than raw compute, which has turned HBM supply into one of the tightest links in the chain.

Advanced packaging and assembly and test. As transistor scaling slows, more of the performance gain now comes from how chips are packaged together. This makes packaging a strategic chokepoint rather than a commodity back-end step. TSMC's CoWoS advanced packaging is itself a capacity constraint for AI accelerators. ASE and Amkor are the leading outsourced assembly and test providers handling chiplet integration.

Layer 4: Semiconductor equipment

Foundries do not build their own tools. They buy them from a small group of equipment makers, often called the wafer-fab-equipment vendors. Several of these hold near-monopoly positions in their specific step of the process, which is the source of their durable margins.

Layer 5: Sub-suppliers and materials

Beneath the equipment makers sits the deepest and least visible layer, the firms that supply the equipment vendors themselves and the consumable materials every fab burns through. The moats here can be the widest in the entire chain precisely because these companies are so specialized.

ASML's own suppliers. Zeiss is the exclusive supplier of the precision optics inside every EUV system, arguably one of the most irreplaceable companies in technology, though its semiconductor unit is privately held. Trumpf supplies the high-power lasers, and Cymer is the light-source unit ASML acquired.

Consumable materials. Photoresists and process chemicals from JSR, Tokyo Ohka Kogyo, Shin-Etsu, and DuPont. Silicon wafers from Shin-Etsu and SUMCO, the two dominant wafer suppliers. Specialty gases, deposition precursors, and polishing slurries from Entegris, Linde, and Air Liquide.

Part III. Cross-cutting layers

Some of the most important parts of the AI buildout do not sit neatly on the top-to-bottom silicon ladder. They cut across it, and several have become binding constraints in their own right.

Power and cooling. Vertiv, Eaton, and Schneider Electric, along with the broader generation and grid supply chain. Electricity delivery and heat removal are increasingly the real limit on how fast data centers can grow.

Networking and interconnect. Optical transceiver and component makers such as Coherent, Lumentum, and Fabrinet, which move data between thousands of accelerators.

Data center real estate. Equinix and Digital Realty, the REITs that own the physical footprint AI compute runs in.

Part IV. How a chip is actually made

To understand why the lower layers carry such pricing power, it helps to see what the manufacturing process actually involves. Production splits into three broad phases: design, the front-end (building the circuits on the wafer), and the back-end (cutting the wafer apart and packaging the chips). The front-end is the part that requires the most exotic equipment and the cleanest facilities, and it is where the equipment and materials suppliers earn their position.

Phase 1: Design and mask making

Engineers lay out the circuit using design-automation software from Cadence or Synopsys, often building on licensed Arm cores or other IP blocks. The finished layout is turned into photomasks, the precision templates that define each layer of the circuit. A pattern is written onto a glass plate coated with a light-blocking film, then etched so that only the intended circuit pattern remains. These masks act as the stencils for the lithography step that follows.

Phase 2: Front-end, building the circuit on the wafer

The front-end is a cycle of steps repeated many times, layer by layer, to build up transistors and the metal wiring that connects them. A modern logic chip can require dozens of such cycles. The core loop looks like this:

1. Wafer preparation. A polished silicon wafer, sliced from a single crystal ingot, is cleaned to remove any contamination.
2. Oxidation and film deposition. A thin film, often an insulating oxide, is grown or deposited on the surface. Deposition tools from Applied Materials, Lam Research, and Tokyo Electron handle this step.
3. Photoresist coating. A light-sensitive chemical called photoresist, supplied by firms like JSR and Tokyo Ohka Kogyo, is spun across the wafer in an even layer.
4. Lithography (exposure). Light is projected through the photomask onto the resist, transferring the circuit pattern. On advanced nodes this is done with ASML's extreme ultraviolet systems, whose optics come from Zeiss.
5. Development and etch. The exposed resist is developed away, and etching tools remove the underlying material where it is no longer protected, carving the pattern into the film.
6. Doping. Impurities are introduced, by diffusion or ion implantation, to give regions of the silicon the electrical properties that make a transistor work.
7. Deposition of wiring layers and planarization. Metal interconnect layers are added and polished flat using chemical-mechanical planarization, which relies on slurries from suppliers such as Entegris.
8. Inspection and metrology. Throughout the flow, KLA's inspection and measurement tools check for defects and police yield. The whole loop then repeats for the next layer.

Because each of these steps is dominated by one or a few specialized vendors, a single weak link can constrain the entire industry. This is the structural reason the equipment and materials layers hold such leverage.

Phase 3: Back-end, dicing, packaging, and test

Once the wafer is complete, the individual chips, still arrayed on the wafer, must be separated, protected, and connected to the outside world.

1. Wafer probe. Each die is electrically tested while still on the wafer so that defective ones can be marked before any further cost is added.
2. Dicing. The wafer is cut into individual dies, increasingly with lasers rather than saw blades as chips get thinner.
3. Die bonding and packaging. Each die is mounted to a substrate that bridges the microscopic chip to the macroscopic circuit board. In advanced packaging, multiple dies and HBM stacks are integrated together, the step where TSMC's CoWoS and the OSAT firms ASE and Amkor operate.
4. Wire bonding or flip-chip interconnect. Electrical connections are made between the die and the package.
5. Final test and burn-in. The packaged chip is tested against its datasheet, often under stress, using systems from Advantest and Teradyne, then marked and shipped.

Part V. A framework for where the economics sit

Walking the stack is only half the exercise. The investment question is where, along this chain, the economics are most durable. A few lenses help.

Count the players at each layer. As a rough rule, pricing power rises as the number of viable suppliers falls. The application layer is crowded; the EUV-optics layer is effectively a single company. Mapping how many credible competitors exist at each step is the fastest way to spot where margins are defensible.

Margin profile versus cyclicality. The deeper layers often carry the widest moats but also the sharpest cyclicality, because they sit furthest from the end customer and feel the full swing of the capital spending cycle. A position that looks like a monopoly during a buildout can still see revenue fall hard when wafer starts pause.

Concentration and geopolitical risk. The leading edge of manufacturing is concentrated in Taiwan and South Korea, which introduces a layer of geopolitical risk that has no equivalent at the application level. Export controls on advanced lithography, government subsidy programs, and efforts to build domestic capacity all reshape the competitive map in ways that cut across the financial analysis.

How much is already priced in. Every layer trades on expectations. The same monopoly position can be a great investment or a poor one depending on the multiple already attached to it. The map tells you where the durable businesses are; valuation discipline tells you whether they are worth owning today.

Part VI. Representative tickers by layer

The table below maps the names above to their primary listings. Many of the deepest-moat suppliers are foreign-listed, privately held, or accessible mainly through American depositary receipts, which is worth remembering before assuming a company is investable. This is a map of who sits where, not a list of recommendations.

A few notes on what is not cleanly investable. Zeiss's semiconductor optics unit and Trumpf are both privately held, so there is no direct equity. JSR was taken private by Japan Investment Corporation in 2024 and no longer trades. Cymer is owned inside ASML. The hyperscalers' in-house silicon efforts, Google's TPU and Amazon's Trainium among them, are not standalone businesses, so exposure to them comes only through the parent.

Part VII. ETFs that map to the stack

For investors who would rather own a layer than a single name, a handful of exchange-traded funds line up reasonably well against this map. None is a pure play on any one tier, and the broad semiconductor funds overlap heavily with one another, so the practical question is usually how much single-name concentration and how much foreign exposure you want.

Broad semiconductors, including designers, foundries, and equipment. The two largest are the VanEck Semiconductor ETF (SMH) and the iShares Semiconductor ETF (SOXX). SMH is the more concentrated of the two and the more global, holding TSMC and ASML directly alongside a heavy Nvidia weighting, which makes it the closest thing to a single fund that spans designers, the leading foundry, and the lithography monopoly at once. SOXX is more U.S.-centric and spreads weight across roughly 30 names under a modified cap-weighting that deliberately tones down the megacaps. The Invesco PHLX Semiconductor ETF (SOXQ) covers similar ground at a lower expense ratio.

Tilts away from the megacaps. The SPDR S&P Semiconductor ETF (XSD) uses equal weighting, which pushes exposure toward smaller equipment, memory, and analog names that the cap-weighted funds barely register. The First Trust Nasdaq Semiconductor ETF (FTXL) and the Invesco Semiconductors ETF (PSI) use factor screens that similarly lift mid-cap equipment and connectivity names. These are the closest available proxies for the lower, deeper-moat layers of the stack, since no clean pure-play equipment or memory ETF trades in the United States.

The cross-cutting layers. Power, cooling, and the data center buildout have their own thematic funds. The VanEck Data Center Supply Chain ETF (RACK), launched in mid-2026, targets the semiconductors, power, cooling, and grid equipment behind AI infrastructure specifically. The Defiance AI & Power Infrastructure ETF (AIPO) leans toward the power-generation and electrical-infrastructure side, and the First Trust NASDAQ Clean Edge Smart Grid Infrastructure ETF (GRID) captures grid and electrical equipment more broadly.

As always, expense ratios, holdings, and even the existence of newer funds shift over time, so it is worth pulling a current fact sheet before acting on any of these.

Closing thought

The AI supply chain rewards investors who understand that the most visible names at the top are not always where the most durable economics live. The further down you look, the fewer the players and the wider the moat, but also the sharper the cycle. A top-down map is valuable precisely because it forces you to see the whole structure at once, and to decide deliberately which layer you actually want exposure to.

This piece is for informational purposes only and is not investment advice. Company standings, process nodes, and fund details move quickly; verify current facts before making any decision.